HyperScale Data Center Connectivity in 100G, 200G, and 400G Networks
Santa Clara, Calif., May 1, 2018 – Credo, a global innovation leader in Serializer-Deserializer (SerDes) technology, today announced it will demonstrate its advanced high performance, low power SerDes IP offerings at this week’s TSMC Technology Symposium, featuring single-lane rate 112G PAM4 and single-lane rate 56Gbps PAM4.
The wide range of Credo SerDes IP solutions enables ASIC, ASSP, and SoC designers to meet the power and performance requirements of a variety of applications including switching, general purpose computing, artificial intelligence, and machine learning all of which are fueling expansion in next generation data center, enterprise, and telco networks.
WHERE: TSMC Open Innovation Platform Ecosystem Forum
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054
Booth # 403
WHEN: May 1, 2018 at 8:30 a.m. – 5:30 p.m.
WHAT: The TSMC Technology Symposium brings together TSMC's design ecosystem companies and our customers to share practical, tested solutions to today's design challenges. Success stories that illustrate TSMC's design ecosystem best practices highlight the event.
Credo is a leading provider of high performance, mixed-signal semiconductor solutions for the data center, enterprise networking and high performance computing markets. Credo's advanced Serializer-Deserializer (SerDes) technology delivers the bandwidth scalability and end-to-end signal integrity for next generation platforms requiring single-lane 25G, 50G, and 100G connectivity. The company makes its SerDes available in the form of Intellectual Property (IP) licensing on the most advanced process nodes and with complementary product families focused on extending reach and multiplexing to higher data rates. Credo has offices in Milpitas, Taiwan, Shanghai and Hong Kong.
For more information: www.credosemi.com
Press Contact: Jen Peckham, email@example.com