Careers

Engineering

Hardware Engineer Milpitas, CA

Description:

  • PCB Design, Layout review, system bring-up and debugging in the lab. 

Qualification:

  • MS in Electrical Engineering;
  • 5+ years in designing boards and FPGA with Verilog;
  • Experience with Orcad/Allegro and layout supervision;
  • Good understanding of signal integrity and layout simulation tools like Sigrity PowerSI or Ansys HFSS
  • System bring-up and debug in lab. Usage of Oscilloscopes, Logic Analyzers and debug tools like Realview, Chipscope;
  • Self-driven and motivated to work in an active environment.

 

System Design Manager | Milpitas, CA

Description:

  • Advising lab manager and test engineers regarding selection of test equipment;
  • Defining test platforms based on different test requirements from different specifications, such as IEEE or CEI specifications;
  • Establishing testing plans, including setting the test conditions, requirements and schedule;
  • Bringing up the silicon, that is, compare its actual functioning to the specifications set previously to ensure that it was created according to the standards set;
  • Building the test automation system using Python to automate the testing of equipment and the functioning of the thermo-stream;
  • Optimizing block-level Analog front-end and DSP performance including signal detector, CDR, CTLE, DFE, and FFE characterization;
  • Measuring the silicon performance by generating system-level characterization, including power characterization, BER characterization and link up stress test;
  • Managing the documentation of the validation results until silicon goes to production by generating the report and documenting all the detailed test conditions, test setup and test results;
  • Utilizing feedback from application engineers to debug issues with customer's platforms; Tuning the internal knobs and registers of the silicon to enhance specific performance requirements of different customers.

Qualification:

  • Master’s degree in Electrical Engineering, plus 36 months of experience as system design manager, system design engineer or related. 
  • Mail resume to Haoli Qian, Credo Semiconductor, 1900 McCarthy Blvd. Suite, Milpitas, 95035.

 

Physical Design Engineer | Milpitas, CA

Description:

  • Perform RTL to GDSII design flow, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, EM/IR;
  • Perform Full chip DRC/LVS;
  • Automate the design flow to promote efficienncy,improve RTL to GDS design flow;
  • Participate in next generation physical design, methodology and flow development.

Qualification:

  • BSEE/MSEE with minimum 1-year of P&R experience by using  SoC Encounter;
  • Successful track records of taping out 40/28/16 nm chips;
  • Familiar with DC,TEMPUS,DFT is prefer;
  • Be familiar with RTL to GDSII design flow;
  • Be familiar with EDA tool, such as ICC or Soc encounter;
  • Be familiar with computer languages such as Perl/TCL/C-shell;
  • Self-motivated with good communication skills and team spirit.

 

Physical Design Manager | Milpitas, CA

Description:

  • Implementing from Synthesis to GDSII that includes synthesis/Scan Insertion/P&R/ timing; signoff/physical signoff and all variety check for Higher QoR;
  • Power fixing based on power analysis result;
  • Develop methodologies to make daily work more efficient;
  • Cooperate with designers on RTL issues which relative to backend timing closure and congestion solve;
  • Debugging the flow to make it advance;
  • Can lead a small team for project implement.

Qualification:

  • Candidate is preferred to be MSEE with minimum of 5 years, or BSEE with minimum of 7-year experience in digital ASIC/SOC Physical design;
  • As a Key team member, can help to execute plans, and mentor fresh people in daily work;
  • Have DRC/LVS/ERC/Antenna debugging skills;
  • Knows Cadence Implement flow such as Genus/Innovus flow;
  • Good programming skill;
  • Understanding the DFT concept w/ scan chain insertion;
  • Knows low power methodologies for BE implement;
  • Capable of writing TCL or Perl;
  • Familiar with synthesis, static timing analysis, Understanding timing signoff w/ Primetime or Tempus;
  • Familiar with RTL Design in Verilog is a plus;
  • Self-motivated team worker, good verbal and written communication skills in English.

 

DFT Engineer | Milpitas, CA

Description:

  • Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SoC design;
  • Generating, simulation and debugging the test patterns for ATE manufacture testing;
  • Interface with back-end physical design team to complete timing closure for test related logic;
  • Interface with operation team to debug production test-vectors for wafer test and final test.

Qualification:

  • BSEE/MSEE major in EE or related discipline;
  • Strong experience in ASIC logic design and verification;
  • 3+ years work experience in ASIC DFT design;
  • Logical thinking and sensitive to the problem with good self-study and problem shooting ability;
  • Good communication capability and teamwork spirit;

Operations

Check back soon as we are expanding and always looking for talented people who "believe" (Credo).

 


Sales & Marketing

Check back soon as we are expanding and always looking for talented people who "believe" (Credo).


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